In the fabrication of a semiconductor integrated circuit device, it is desirable to fabricate the device with materials having a low resistivity (i.e., property of resistance to current flow) in order to optimize the device's electrical performance. Lower resistance within the device allows faster processing of information due to a smaller delay time associated with resistance to current flow.
Various portions of an integrated circuit device are typically interconnected using metal lines (i.e., conductive layers) with metal contacts extending to active areas within the device. Resistivity of the metal lines plays an increasingly important role in the overall resistance of an integrated circuit device. As such devices become more dense, wiring length increases. Furthermore, wiring pitch decreases, which effectively decreases the available wiring width. As the wiring width decreases, resistivity of the wiring material becomes a dominant factor as compared to parasitic capacitance between wires (i.e., that associated with device resistance). Thus, it is desirable to decrease the resistivity of wiring material within an integrated circuit device.
Copper (Cu) and silver (Ag) are becoming increasingly desirable in integrated circuit fabrication as a replacement for aluminum (Al), particularly for interconnect lines and other conductive structures (i.e., conductive digit lines and plugs connecting the conductive layers). Copper and silver have lower resistivity and higher resistance to electromigration (i.e., the transport of metal atoms in conductors carrying large current densities, resulting in morphological degradation of the conductors) than aluminum.
These metal interconnects and contacts are typically formed using a dual damascene technique. In a dual damascene process, a dielectric layer is formed over a semiconductor substrate in which the integrated circuit device is being fabricated. Vias are formed in the dielectric layer to expose active areas of the semiconductor substrate and trenches are formed in the dielectric layer to couple the vias to other portions of the integrated circuit device. A metal layer is then blanket deposited to fill the trenches and vias and to cover the dielectric layer. The excess metal overlying the dielectric layer is removed, such as by chemical-mechanical planarization (CMP) to define the metal interconnects as the metal-filled trenches and metal contacts as the metal-filled vias. A CMP process generally involves abrading the surface of the semiconductor substrate with an abrasive and a solution to chemically assist the abrasive. The abrasive/solution combination is generally specific to the material to be removed and to the surrounding materials to be retained.
To reduce migration or diffusion of copper or silver into the underlying substrate, a diffusion barrier layer is often interposed between the substrate and the metal layer. Tantalum nitride is one material used as a diffusion barrier layer between the substrate and the metal layer. Continuous copper and silver layers are readily formed over tantalum nitride. However, it is generally necessary to use two different abrasive/solution combinations to first remove the copper or silver layer and then remove the tantalum nitride layer. While the use of titanium nitride as a diffusion barrier layer facilitates the use of a single abrasive/solution combination, it can be difficult to form copper or silver layers on a titanium nitride layer. Because of their large surface energies, copper and silver tend to agglomerate on a titanium nitride layer, thus tending to result in a discontinuous film and the production of voids in the damascene structure.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative structures and methods for utilizing copper, silver and other high surface-energy metals as integrated circuit interconnect materials.